A system on a chip, SOC, is designed using high level design units. These units, also known as cores or macros, are created in-house or purchased from a third party. Examples of cores include: embedded processors; busses; memory; external IO; and custom logic. The ideal in-house core is one that is complete and fully verified prior to using it in an SOC. If the core is not available, a third party core is sought. The third party core is a highly specialized intellectual property core that ideally plugs into the SOC design. If all the cores are functionally correct and they work well with each other, then the process of creating SOCs simply involves connecting cores together. However the reality is that this is usually not the case and most designs require extensive in-circuit testing.
When doing in-circuit testing, the desired goal is to feed the chip with real world stimuli throughout the operating range; this type of testing is commonly called shmoo testing. It is through shmoo testing that complete confidence in the SOC design is obtained. SOC's are typically tested by manufacturing a prototype printed circuit board, PCB, containing the SOC design. Often, the prototype PCB design employs a field programmable gate array (FPGA) in place of an ASIC. FPGAs are used for the re-programmability, which lends itself well to a test and repair loop often iterated during chip turn on.
FPGAs are extremely useful integrated circuits (ICs) employed by electronics designers in a multitude of industrial and consumer electronic products to implement a considerable amount of digital circuitry within a small area. The use of these circuits normally provides fast, reliable, compact functionality to any device in which they reside. The designer typically defines the integrated circuitry using a programming language, and then employs readily available software to compile the circuit definition into a form of data used to program an FPGA with the functions specified by the designer.
Bench top instruments, like oscilloscopes and logic analyzers, are important tools used during in-circuit test. Many digital designers are accustomed to bringing up their prototype boards using a logic analyzer as a debug aid. They use the logic analyzer to help uncover integration issues as well as design errors. To observe the behavior of the system, the designer probes various buses and chips in an attempt isolate the root cause of the problem. It is through this probing and re-probing of various components, that enough information may be gathered to properly assess the factors leading to the problem. With this information it is possible for the engineering team to understand the error and formulate a solution.
From a testing perspective, most FPGAs have a limited number of power, input, and output pins, especially when compared to the amount of signals that exist within an FPGA. This limits the external visibility of most of the signals to electronic test and measurement equipment. In most cases, the designer can view only a few internal signals of interest that are connected to a limited number of dedicated debug pins on the FPGA package. To analyze another group of signals, the circuit definition must be modified to disconnect the previously viewed signals from the debug pins and new signals of interest rerouted to those pins. The new circuit definition must then be recompiled and the FPGA re-programmed. Every time a new set of signals is to be probed, the foregoing process is repeated. As a result, debugging a design can become a painstaking, time-consuming, and error-prone process.
Additionally, each design compilation has the potential of subtly altering the timing characteristics of the FPGA because of changes in signal routing and capacitive loading. The mere process of recompiling the FPGA, even with seemingly minor changes, has the potential to inject non-deterministic timing issues that could cause the design to operate incorrectly, thus requiring further design changes and recompilation.
The present inventors have recognized a need for circuits and methods that provides an FPGA designer with a flexible approach to analyzing the internal signals of a FPGA and in particular FPGA used with SOC designs.